An interleaved array-processing architecture

Authors:
J. R. Jump;J. D. Wise;D. T. Harper, III
Affiliations:
Rice University, Houston, Texas;Rice University, Houston, Texas;Rice University, Houston, Texas
Venue:
AFIPS '84 Proceedings of the July 9-12, 1984, national computer conference and exposition
Year:
1984

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Abstract

This paper describes an array-processing architecture capable of executing high-level vector operations. There are two distinguishing features of this architecture: First, the user can define for later use complex vector operations that involve several arithmetic operations and branching. Once defined, they appear as built-in vector instructions to the user. Second, the algorithms for accessing and aligning vectors are implemented in hardware, eliminating the need for user programs to deal with memory addresses.