A modular memory scheme for array processing

Authors:
S. R. Ahuja;J. R. Jump
Affiliations:
Department of Electrical Engineering, Rice University, Houston, Texas;Department of Electrical Engineering, Rice University, Houston, Texas
Venue:
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
Year:
1977

Citing 2
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AFIPS '84 Proceedings of the July 9-12, 1984, national computer conference and exposition

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Abstract

This paper presents a parallel memory scheme suited for pipelined processing units. The scheme is shown to be modular, relatively low cost and flexible. The scheme allows an arbitrary number of variables in the vector operations. It is shown that data alignment is handled by a simple interconnection scheme and that the interconnection scheme can be implemented in the memory modules. It is shown that the scheme facilitates efficient implementation of the Perfect Shuffle interconnection, hence the implementation of parallel algorithms using that interconnection scheme.