Exact performance estimates for multiprocessor memory and bus interference
IEEE Transactions on Computers
Effective Memory Bandwidth and Processor Blocking Probability in Multiple-Bus Systems
IEEE Transactions on Computers
Analysis of prioritized crossbar multiprocessor systems
Journal of Parallel and Distributed Computing
Computer Architecture and Parallel Processing
Computer Architecture and Parallel Processing
Probabilistic analysis of a crossbar switch
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
Performance Modeling and Evaluation of Circuit Switching Using Clos Networks
IEEE Transactions on Computers
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A comprehensive model for evaluating crossbar networks in which the memory bandwidth and processor acceptance probability are primary measures considered is presented. This analytical model includes all important network control policies, such as the bus arbitration and rejected request handling policies, as well as the home memory concept. Computer simulation validates the correctness of the model. It is confirmed that the home memory and dynamic bus arbitration policy improve the network performance.