A Multiprocessor Bus Design Model Validated by System Measurement

  • Authors:
  • T. F. Tsuei;M. K. Vernon

  • Affiliations:
  • -;-

  • Venue:
  • IEEE Transactions on Parallel and Distributed Systems
  • Year:
  • 1992

Quantified Score

Hi-index 0.00

Visualization

Abstract

An accurate and efficient model of a commercial multiprocessor bus is developed. Fourimportant characteristics of the bus design are modeled: asynchronous memory writeoperations; in-order delivery of responses to processor read requests; priority schedulingof memory responses; and upper bounds on the number of outstanding processorrequests. A two-level hierarchical model employing both Markov chain and mean valueanalysis techniques for analyzing queueing networks is used. The model is shown toaccurately predict measured system performance for two parallel program workloads thathave different memory access characteristics. The results provide evidence that analyticqueueing models can be extremely accurate in spite of simplifying assumptions requiredfor model tractability. Model estimates are compared against detailed simulation of thebus to investigate in more detail the likely source of small model inaccuracies. The use ofthe analytical model for assessing system design tradeoffs is illustrated.