Exact performance estimates for multiprocessor memory and bus interference
IEEE Transactions on Computers
Attributes of the performance of central processing units: a relative performance prediction model
Communications of the ACM
A simulation study of two-level caches
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
A mean-value performance analysis of a new multiprocessor architecture
SIGMETRICS '88 Proceedings of the 1988 ACM SIGMETRICS conference on Measurement and modeling of computer systems
The technology of parallel processing: parallel processing architectures and VLSI hardware (vol. 1)
The technology of parallel processing: parallel processing architectures and VLSI hardware (vol. 1)
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Cache and memory hierarchy design: a performance-directed approach
Cache and memory hierarchy design: a performance-directed approach
Modeling and measurement of the impact of Input/Output on system performance
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
Markovian Queueing Network Models for Performance Analysis of a Single-Bus Multiprocessor System
IEEE Transactions on Computers
Evaluating Design Choices for Shared Bus Multiprocessors in a Throughput-Oriented Environment
IEEE Transactions on Computers
A Model of Workloads and its Use in Miss-Rate Prediction for Fully Associative Caches
IEEE Transactions on Computers
The Operational Analysis of Queueing Network Models
ACM Computing Surveys (CSUR)
A Multiprocessor Bus Design Model Validated by System Measurement
IEEE Transactions on Parallel and Distributed Systems
Performances Modeling and Evaluation for the XMP Shared-Bus Multiprocessor Architecture
Proceedings of the 1994 International Conference on Parallel and Distributed Systems
Proceedings of the Conference on Design, Automation and Test in Europe
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A methodology, called Subsystem Access Time (SAT) modeling, is proposed for the performance modeling and analysis of shared-bus multiprocessors. The methodology is subsystem-oriented because it is based on a Subsystem Access Time Per Instruction (SATPI) concept, in which we treat major components other than processors (e.g., off-chip cache, bus, memory, I/O) as subsystems and model for each of them the mean access time per instruction from each processor.The SAT modeling methodology is derived from the Customized Mean Value Analysis (CMVA) technique, which is request-oriented in the sense that it models the weighted total mean delay for each type of request processed in the subsystems. The subsystem-oriented view of the proposed methodology facilitates divide-and-conquer modeling and bottleneck analysis, which is rarely addressed previously. These distinguishing features lead to a simple, general, and systematic approach to the analytical modeling and analysis of complex multiprocessor systems.To illustrate the key ideas and features that are different from CMVA, an example performance model of a particular shared-bus multiprocessor architecture is presented. The model is used to conduct performance evaluation for throughput prediction. Thereby, the SATPIs of the subsystems are directly utilized to identify the bottleneck subsystem and find the requests or subsystem components that cause the bottleneck. Furthermore, the SATPIs of the subsystems are employed to explore the impact of several performance influencing factors, including memory latency, number of processors, data bus width, as well as DMA transfer.