Exact performance estimates for multiprocessor memory and bus interference
IEEE Transactions on Computers
Vector Computer Memory Bank Contention
IEEE Transactions on Computers
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One of the major factors influencing the performance of an interleaved memory system is the behavior of the request sequence, but this is normally ignored. This paper examines this issue. Using trace driven simulations it is shown that the commonly used assumption, that each request is independently and equally likely to be to any module, is not valid. The duality of memory interference with paging behavior is noted and this suggests the use of the least-recently used stack model to model program behavior. Simulations indicate that this model is reasonably accurate. An accurate, though approximate, expression for the bandwidth is derived based upon this model.