Analysis of vector access performance on skewed interleaved memory

Authors:
C.-L. Chen;C.-K. Liao
Affiliations:
Department of Computer Science, and Information Engineering, National Taiwan University, Taipei, Taiwan, R.O.C.;Institute of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C.
Venue:
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Year:
1989

Citing 4
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Abstract

Memory interleaving and memory skewing are two hardware approaches to reduce memory access conflict for many advanced computer architectures, while pipelined vector computer covers many commercially available supercomputers. The goal of this paper is to study the vector accessing behavior on skewed interleaved memory under pipelined processing environment.We establish a criterion, called average time delay, to indicate the performance of a vector access; and a criterion, called aggregate average time delay to indicate the performance of a given memory system. Under these criteria, we analyze some memory design problems. These problems centralize how to design a memory system which is cost-effective and has less conflicts for vector accesses.We also propose a software approach to reduce memory access conflict, called dimension extension strategy. This strategy performs very well under our analysis.