On the effective bandwidth of interleaved memories in vector processor systems
IEEE Transactions on Computers
A Simulation Study of the CRAY X-MP Memory System
IEEE Transactions on Computers
Classification Categories and Historical Development of Circuit Switching Topologies
ACM Computing Surveys (CSUR)
Characterizing Computers and Optimizing the FACR(l) Poisson-Solver on Parallel Unicomputers
IEEE Transactions on Computers
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This paper describes investigations on the memory performance of the shared memory systems Cray X-MP and Cray Y-MP. Single and multiple CPU performance will be considered and special emphasis will be put on performance differences that result from differences in the interconnect network between memory and CPUs of both machines. Measurement results for kernels and application programs are presented to demonstrate the impact of these architectural changes. The effect of memory contention will be studied for codes with even stride memory access that utilize only part of the available memory banks.