OMP: a RISC-based multiprocessor using orthogonal-access memories and multiple spanning buses

Authors:
K. Hwang;M. Dubois;D. K. Panda;S. Rao;S. Shang;A. Uresin;W. Mao;H. Nair;M. Lytwyn;F. Hsieh;J. Liu;S. Mehrotra;C. M. Cheng
Affiliations:
Laboratory for Parallel and Distributed Computing, University of Southern California, Los Angeles, CA;Laboratory for Parallel and Distributed Computing, University of Southern California, Los Angeles, CA;Laboratory for Parallel and Distributed Computing, University of Southern California, Los Angeles, CA;Laboratory for Parallel and Distributed Computing, University of Southern California, Los Angeles, CA;Laboratory for Parallel and Distributed Computing, University of Southern California, Los Angeles, CA;Laboratory for Parallel and Distributed Computing, University of Southern California, Los Angeles, CA;Laboratory for Parallel and Distributed Computing, University of Southern California, Los Angeles, CA;Laboratory for Parallel and Distributed Computing, University of Southern California, Los Angeles, CA;Laboratory for Parallel and Distributed Computing, University of Southern California, Los Angeles, CA;Laboratory for Parallel and Distributed Computing, University of Southern California, Los Angeles, CA;Laboratory for Parallel and Distributed Computing, University of Southern California, Los Angeles, CA;Laboratory for Parallel and Distributed Computing, University of Southern California, Los Angeles, CA;Laboratory for Parallel and Distributed Computing, University of Southern California, Los Angeles, CA
Venue:
ICS '90 Proceedings of the 4th international conference on Supercomputing
Year:
1990

Citing 5
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Abstract

This paper presents the architectural design and RISC based implementation of a prototype supercomputer, namely the Orthogonal MultiProcessor (OMP). The OMP system is constructed with 16 Intel 1860 RISC microprocessors and 256 parallel memory modules, which are 2-D interleaved and orthogonally accessed using custom-designed spanning buses. The architectural design has been validated by a CSIM-based multiprocessor simulator. The design choices are based on worst-case delay analysis and simulation validation. The current OMP prototype chooses a 2-dimensional memory architecture, mainly for image processing, computer vision, and neural network simulation applications. The 16-processor OMP prototype is targeted to achieve a peak performance of 400 RISC integer MIPS or a maximum of 640 Mflops. This paper presents the architectural design of the OMP prototype at system and PC board levels. We are presently entering the fabrication stage of all the PC boards. The system is expected to become operational in late 1991 and benchmarking results will be available in 1992. Only hardware design features are reported here. Software and simulation results are reported elsewhere.