The bandwidth expansion effectiveness of cache levels block prefetch

Authors:
Youngkwan Ju;Bongyong Uh;Sukil Kim
Affiliations:
Dept. of Computer Science, Chungbuk National University, Cheongju, Chungbuk, Republic of Korea;Dept. of Computer Science, Chungbuk National University, Cheongju, Chungbuk, Republic of Korea;Dept. of Computer Science, Chungbuk National University, Cheongju, Chungbuk, Republic of Korea
Venue:
ISHPC'05/ALPS'06 Proceedings of the 6th international symposium on high-performance computing and 1st international conference on Advanced low power systems
Year:
2005

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Abstract

Most cache architectures exploit only a second level cache prefetch. In this paper, we propose the hierarchical prefetch cache architecture which allows prefetch between all levels of caches. We discovered that this architecture has a virtual effect of expanding memory bus bandwidth. According to an experimental analysis using 10 benchmark programs, the proposed architecture that employs all level cache prefetcher obtained a maximum 11% increased performance when compared to both architecture with expanded bus bandwidth and architecture with employment only a level 2 cache prefetcher. This shows our proposed architecture has an effectiveness of memory-bus bandwidth expansion.