Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
Hierarchical Parallelization of an H.264/AVC Video Encoder
PARELEC '06 Proceedings of the international symposium on Parallel Computing in Electrical Engineering
HD-VideoBench. A Benchmark for Evaluating High Definition Digital Video Applications
IISWC '07 Proceedings of the 2007 IEEE 10th International Symposium on Workload Characterization
CASES '10 Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems
A QHD-capable parallel H.264 decoder
Proceedings of the international conference on Supercomputing
Journal of Systems Architecture: the EUROMICRO Journal
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In previous work the 3D-Wave parallelization strategy was proposed to increase the parallel scalability of H.264 video decoding. This strategy is based on the observation that inter-frame dependencies have a limited spatial range. The previous results, however, investigate application scalability on an idealized multiprocessor. This work presents an implementation of the 3D-Wave strategy on a multicore architecture composed of NXP TriMedia TM3270 embedded processors. The results show that the parallel H.264 implementation scales very well, achieving a speedup of more than 54 on a 64-core processor. Potential drawbacks of the 3D-Wave strategy are that the memory requirements increase since there can be many frames in flight, and that the latencies of some frames might increase. To address these drawbacks, policies to reduce the number of frames in flight and the frame latency are also presented. The results show that our policies combat memory and latency issues with a negligible effect on the performance scalability.