An FPGA architecture for CABAC decoding in manycore systems

Authors:
Roberto R. Osorio;Javier D. Bruguera
Affiliations:
University of Santiago de Compostela, Dept. Electronics and Computer Science, Spain;University of Santiago de Compostela, Dept. Electronics and Computer Science, Spain
Venue:
ASAP '08 Proceedings of the 2008 International Conference on Application-Specific Systems, Architectures and Processors
Year:
2008

Citing 0
Cited 3

CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey

SAMOS '09 Proceedings of the 9th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
A highly scalable parallel implementation of h.264

Transactions on High-Performance Embedded Architectures and Compilers IV
High-Speed FPGA Architecture for CABAC Decoding Acceleration in H.264/AVC Standard

Journal of Signal Processing Systems

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Abstract

Arithmetic coding is an efficient entropy compression method that achieves results close to the entropy limit and it is used in modern standards such as JPEG-2000 and H.264. Arithmetic decoding (AD) in H.264 video coding standard is a sequential task that takes a significant part of computing time. In present and future multicore and manycore systems, AD becomes a bottleneck as it cannot be parallelized, limiting the concurrent execution of other tasks. In this paper, an FPGA-based accelerator is proposed to speed-up AD in H.264 and enable parallel decoding at macroblock and frame levels scaling up to tens or hundreds of cores.