Fast Frame/Field Coding for H.264/AVC
ICDT '06 Proceedings of the international conference on Digital Telecommunications
A high performance CABAC decoding architecture
IEEE Transactions on Consumer Electronics
Overview of the H.264/AVC video coding standard
IEEE Transactions on Circuits and Systems for Video Technology
Context-based adaptive binary arithmetic coding in the H.264/AVC video compression standard
IEEE Transactions on Circuits and Systems for Video Technology
Review: H.264 video transmissions over wireless networks: Challenges and solutions
Computer Communications
Joint Algorithm-Architecture Optimization of CABAC
Journal of Signal Processing Systems
High-Speed FPGA Architecture for CABAC Decoding Acceleration in H.264/AVC Standard
Journal of Signal Processing Systems
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In this letter we propose a high-throughput VLSI architecture design for H.264 high-profile context-based adaptive binary arithmatic coding (HP CABAC) decoding for HDTV applications. To speed up the inherent sequential CABAC decoding, we eliminate the bottleneck by proposing a look-ahead decision parsing technique on the grouped context table with cache registers, which reduces 62% of cycle count on average as compared with the original CABAC decoding. In addition, the proposed design supports the macroblock adaptive frame field coding tools in H.264 main profile coding and 8 × 8 transform in H.264 high-profile coding. It achieves the real-time processing for H.264 CABAC decoding up to L4.1@30 frames/s with maximum 60 Mbits/s when operating at 105 MHz.