High-throughput H.264/AVC high-profile CABAC decoder for HDTV applications
IEEE Transactions on Circuits and Systems for Video Technology
Variable-bin-rate CABAC engine for H.264/AVC high definition real-time decoding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multicore processing and efficient on-chip caching for H.264 and future video decoders
IEEE Transactions on Circuits and Systems for Video Technology
A high throughput CABAC algorithm using syntax element partitioning
ICIP'09 Proceedings of the 16th IEEE international conference on Image processing
A high-performance hardwired CABAC decoder for ultra-high resolution video
IEEE Transactions on Consumer Electronics
Context-based adaptive binary arithmetic coding in the H.264/AVC video compression standard
IEEE Transactions on Circuits and Systems for Video Technology
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This paper uses joint algorithm and architecture design to enable high coding efficiency in conjunction with high processing speed and low area cost. Specifically, it presents several optimizations that can be performed on Context Adaptive Binary Arithmetic Coding (CABAC), a form of entropy coding used in H.264/AVC, to achieve the throughput necessary for real-time low power high definition video coding. The combination of syntax element partitions and interleaved entropy slices, referred to as Massively Parallel CABAC, increases the number of binary symbols that can be processed in a cycle. Subinterval reordering is used to reduce the cycle time required to process each binary symbol. Under common conditions using the JM12.0 software, the Massively Parallel CABAC, increases the bins per cycle by 2.7 to 32.8脳 at a cost of 0.25 to 6.84% coding loss compared with sequential single slice H.264/AVC CABAC. It also provides a 2脳 reduction in area cost, and reduces memory bandwidth. Subinterval reordering reduces the critical path delay by 14 to 22%, while modifications to context selection reduces the memory requirement by 67%. This work demonstrates that accounting for implementation cost during video coding algorithms design can enable higher processing speed and reduce hardware cost, while still delivering high coding efficiency in the next generation video coding standard.