Joint Algorithm-Architecture Optimization of CABAC
Journal of Signal Processing Systems
High-Speed FPGA Architecture for CABAC Decoding Acceleration in H.264/AVC Standard
Journal of Signal Processing Systems
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Context-Based Binary Arithmetic Coding (CABAC) is one of two entropy coders used in H.264/AVC, which achieves a high compression ratio at the expense of high computational complexity. For real-time decoding of ultra-high resolution video, we propose a high-throughput hardwired CABAC decoder subsystem. By analyzing the distribution of different types of syntax elements (SE), we propose a Two-Bin arithmetic decoding engine (Two-Bin AE) to generate two bins in one cycle for the most frequent SEs. In order to boost the utilization of the proposed engine, we employ a Prediction-Based Parallel Processing Method to perform decoding and context index calculation in parallel. Furthermore, we propose a Context Table Reallocation Scheme, which can shorten the critical path delay of a Two- Bin AE circuit by 18%. Experimental results show that our decoder on average takes only 118 clock cycles to decode one macroblock (MB) at Main Profile, Level 4.0. For QFHD, i.e., 4x1080 HD, sequences, it can run effectively at 110 MHz. The design has been successfully integrated into an H.264/AVC QFHD video decoder in an SOC system.