A high performance CABAC decoding architecture
IEEE Transactions on Consumer Electronics
An efficient VLSI architecture of VLD for AVS HDTV decoder
IEEE Transactions on Consumer Electronics
Context-based adaptive binary arithmetic coding in the H.264/AVC video compression standard
IEEE Transactions on Circuits and Systems for Video Technology
High-Speed H.264/AVC CABAC Decoding
IEEE Transactions on Circuits and Systems for Video Technology
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We present a high-performance entropy decoding system for H.264/AVC. This system includes a variable length coding (VLC) decoder, a context-based adaptive binary arithmetic coding (CABAC) decoder, and a run-level converter. Each syntax element above slice data is decoded by VLC decoder within a clock cycle. The CABAC decoder decodes the syntax elements at slice data and below through pipeline mechanism. A run-level converting method is designed and integrated into the system to improve the output efficiency of decoded quantized coefficients. This system can process 574, 712 macroblock/s operating at 300 MHz, quite enough for real-time decoding for H.264/AVC HD level 4.1 video sequences.