FPGA implementation of a parallel EBCOT tier-1 encoder that preserves coding efficiency
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
A Hardware Architecture of CABAC Encoding and Decoding with Dynamic Pipeline for H.264/AVC
Journal of Signal Processing Systems
A low-power delay buffer using gated driver tree
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient VLSI architecture for bit plane encoder of JPEG 2000
ICIP'09 Proceedings of the 16th IEEE international conference on Image processing
Multiresolution HVS and statistically based image coding scheme
Multimedia Tools and Applications
Multiresolution, perceptual and vector quantization based video codec
Multimedia Tools and Applications
Two-Symbol FPGA Architecture for Fast Arithmetic Encoding in JPEG 2000
Journal of Signal Processing Systems
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JPEG 2000 offers critical advantages over other still image compression schemes at the price of increased computational complexity. Hardware-accelerated performance is a key to successful development of real time JPEG 2000 solutions for applications such as digital cinema and digital home theatre. The crucial role in the whole processing plays embedded block coding with optimized truncation because it requires bit-level operations. In this paper, a dedicated architecture of the block-coding engine is presented. Square-based bit-plane scanning and the internal first-in first-out are combined to speed up the context generation. A dynamic significance state restoring technique reduces the size of the state memories to 1 kbits. The pipeline architecture enhanced by an inverse multiple branch selection method is exploited to code two context-symbol pairs per clock cycle in the arithmetic coder module. The block-coding architecture was implemented in VHDL and synthesized for field-programmable gate array devices. Simulation results show that the single engine can process, on average, about 22 million samples at 66-MHz working frequency.