JPEG 2000: Image Compression Fundamentals, Standards and Practice
JPEG 2000: Image Compression Fundamentals, Standards and Practice
Analysis and architecture design of block-coding engine for EBCOT in JPEG 2000
IEEE Transactions on Circuits and Systems for Video Technology
A high-performance architecture for embedded block coding in JPEG 2000
IEEE Transactions on Circuits and Systems for Video Technology
Two-Symbol FPGA Architecture for Fast Arithmetic Encoding in JPEG 2000
Journal of Signal Processing Systems
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Embedded block coding (EBCOT Tier-1) is the most computationally intensive part of the JPEG2000 image coding standard. Past research on fast EBCOT Tier-1 hardware implementations has concentrated on cycle-efficient context formation, and achieve improved throughput at the cost of reduced coding efficiency. In this paper, a new fast EBCOT Tier-1 design called the Split Arithmetic Encoder (SAE) process is presented. The proposed process exploits concurrency to obtain improved throughput with a lower penalty in coding efficiency. The design is for a complete EBCOT Tier-1 process, and considers system-level issues such as the need for buffering. A hardware architecture for the proposed process was developed, realized in VHDL, and synthesized for implementation on an Altera field programmable gate array. Results show, on average, a 55% improvement in processing time over a serial architecture for a set of sixteen test images.