Two-Symbol FPGA Architecture for Fast Arithmetic Encoding in JPEG 2000

  • Authors:

  • Nandini Ramesh Kumar;Wei Xiang;Yafeng Wang

  • Affiliations:

  • Faculty of Engineering and Surveying, University of Southern Queensland, Toowoomba, Australia;Faculty of Engineering and Surveying, University of Southern Queensland, Toowoomba, Australia;Faculty of Engineering and Surveying, University of Southern Queensland, Toowoomba, Australia

  • Venue:
  • Journal of Signal Processing Systems
  • Year:
  • 2012

Quantified Score

Hi-index 0.00

Visualization

Abstract

JPEG 2000 is one of the most popular image compression standards offering significant performance advantages over previous image standards. High computational complexity of the JPEG 2000 algorithms makes it necessary to employ methods that overcomes the bottlenecks of the system and hence an efficient solution is imperative. One such crucial algorithms in JPEG 2000 is arithmetic coding and is completely based on bit level operations. In this paper, an efficient hardware implementation of arithmetic coding is proposed which uses efficient pipelining and parallel processing for intermediate blocks. The idea is to provide a two-symbol coding engine, which is efficient in terms of performance, memory and hardware. This architecture is implemented in Verilog hardware definition language and synthesized using Altera field programmable gate array. The only memory unit used in this design is a FIFO (first in first out) of 256 bits to store the CX-D pairs at the input, which is negligible compared to the existing arithmetic coding hardware designs. The simulation and synthesis results show that the operating frequency of the proposed architecture is greater than 100 MHz and it achieves a throughput of 212 Msymbols/sec, which is double the throughput of conventional one-symbol implementation and enables at least 50% throughput increase compared to the existing two-symbol architectures.