Concurrent Symbol Processing Capable VLSI Architecture for Bit Plane Coder of JPEG2000*
IEICE - Transactions on Information and Systems
A high-performance JPEG2000 architecture
IEEE Transactions on Circuits and Systems for Video Technology
Analysis and architecture design of block-coding engine for EBCOT in JPEG 2000
IEEE Transactions on Circuits and Systems for Video Technology
Parallel embedded block coding architecture for JPEG 2000
IEEE Transactions on Circuits and Systems for Video Technology
Realizing Low-Cost High-Throughput General-Purpose Block Encoder for JPEG2000
IEEE Transactions on Circuits and Systems for Video Technology
VLSI design of memory-efficient, high-speed baseline MQ coder for JPEG 2000
Integration, the VLSI Journal
Design and implementation of an embedded NIOS II system for JPEG2000 tier II encoding
International Journal of Reconfigurable Computing
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Much work has been performed on optimizing the throughput of the block coding system within JPEG2000. However, the question remains as to whether providing parallel simple block coders provides a cheaper method of increasing throughput than complicated optimized block coders. We present the analysis and results for a system on a chip (SoC) software/hardware codesign platform, for parallel coding in JPEG2000 compression standard. We design both a simple and a high performance, optimized peripheral encoder as a hardware accelerator for the JPEG2000 SoC encoding system. The system is implemented on an Altera NIOS II processor with flexible integrated peripheral. We show that there are optimum numbers of parallel block coders and scheduling granularity per row of codeblocks, and that parallel optimized encoders outperform parallel simple encoders. We also demonstrate that the block coding system becomes work starved rather than memory blocked when many parallel coders are present, indicating a discrete wavelet transform bottleneck.