Efficient hardware architecture for EBCOT in JPEG 2000 using a feedback loop from the rate controller to the bit-plane coder

Authors:
Grzegorz Pastuszak
Affiliations:
Institute of Radioelectronics, Warsaw University of Technology, Warsaw, Poland
Venue:
ICIAP'05 Proceedings of the 13th international conference on Image Analysis and Processing
Year:
2005

Citing 4
Cited 0

JPEG 2000: Image Compression Fundamentals, Standards and Practice

JPEG 2000: Image Compression Fundamentals, Standards and Practice
Efficient Rate Control for Motion JPEG2000

DCC '04 Proceedings of the Conference on Data Compression
A high-performance JPEG2000 architecture

IEEE Transactions on Circuits and Systems for Video Technology
Analysis and architecture design of block-coding engine for EBCOT in JPEG 2000

IEEE Transactions on Circuits and Systems for Video Technology

Quantified Score

Hi-index	0.00

Visualization

Abstract

At the low compression ratio, the EBCOT engine of the JPEG 2000 encoder does not have to process all input data to achieve an optimal codestream in the sense of the rate-distortion criteria. This property is exploited in the architecture presented in this paper to allow higher throughputs of the JPEG 2000 encoder. An impact of the code block size and the internal FIFO size on the resultant speed is considered. The architecture is described in VHDL and synthesized for commercial FPGA technology. Simulation results show that at low compression ratios and for FPGA Stratix II devices, the single engine can support HDTV standards.