Design and implementation of an FPGA-Based 1.452-gbps non-pipelined AES architecture

Authors:
Ignacio Algredo-Badillo;Claudia Feregrino-Uribe;René Cumplido
Affiliations:
National Institute for Astrophysics, Optics and Electronics, Sta. Ma. Tonantzintla, Puebla, México;National Institute for Astrophysics, Optics and Electronics, Sta. Ma. Tonantzintla, Puebla, México;National Institute for Astrophysics, Optics and Electronics, Sta. Ma. Tonantzintla, Puebla, México
Venue:
ICCSA'06 Proceedings of the 2006 international conference on Computational Science and Its Applications - Volume Part III
Year:
2006

Citing 4
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Abstract

This work reports a non-pipelined AES (Advanced Encrypted Standard) FPGA (Field Programmable Gate Array) architecture, with low resource requirements. The architecture is designed to work on CBC (Cipher Block Chaining) mode and achieves a throughput of 1.45 Gbps. This implementation is a module of a configuration library for a Cryptographic Reconfigurable Platform (CRP).