Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Architectural Strategies for Implementing an Image Processing Algorithm on XC6000 FPGA
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
The Trianus System and Its Application to Custom Computing
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
New fast recursive algorithms for the computation of discretecosine and sine transforms
IEEE Transactions on Signal Processing
A faster distributed arithmetic architecture for FPGAs
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Reconfigurable Computing for Digital Signal Processing: A Survey
Journal of VLSI Signal Processing Systems
Development of a Run-Time Reconfiguration System with Low Reconfiguration Overhead
Journal of VLSI Signal Processing Systems
A FPGA-based Library for On-Line Signal Processing
Journal of VLSI Signal Processing Systems
Continuous and high coverage self-testing of dynamically re-configurable systems
Parallel Computing - Parallel computing in image and video processing
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
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This article presents a novel FPGA implementation of a two dimensional (8x8) point Discrete Cosine Transform. It is shown how the development of a suitable architectural style can produce high quality circuit designs for a specific technology, in this case the Xilinx XC6200 series of FPGA. Distributed arithmetic and exploitation of parallelism and pipelining are used to produce a DCT implementation on a single FPGA that operates at 25 frames per second with VGA resolution which is the equivalent of 2 Billion Multiplications or additions per second.