On-the-fly conversion of redundant into conventional representations
IEEE Transactions on Computers
Applying an XC6200 to Real-Time Image Processing
IEEE Design & Test
Implementing On Line Arithmetic on PAM
FPL '94 Proceedings of the 4th International Workshop on Field-Programmable Logic and Applications: Field-Programmable Logic, Architectures, Synthesis and Applications
Digital Signal Processing (4th Edition)
Digital Signal Processing (4th Edition)
FPGA-Based Structures for On-Line FFT and DCT
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hi-index | 0.00 |
A library of on-line arithmetic structures is presented. Their ability to produce and consume the most significant digit first allows subsequent computations to begin earlier, shortens the execution time of variable precision and composite operations, and simplifies interconnection networks which can help preserve high clock rates in large digit-serial designs. More importantly, designers can interconnect individual units without designing intermediate structures to reformat data, a luxury that is currently unavailable to FPGA designers wishing to use bit-serial arithmetic. The on-line structures introduced are small, and can be easily combined to yield more powerful blocks. The library's applicability to signal processing applications is demonstrated with the DFT, DCT, and FIR filter. Results indicate high area efficiency and rapid execution speed.