On-the-fly conversion of redundant into conventional representations
IEEE Transactions on Computers
A FPGA-based Library for On-Line Signal Processing
Journal of VLSI Signal Processing Systems
The effect of reconfigurable units in superscalar processors
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
BigSky-An On-Line Arithmetic Design Tool for FPGAs
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
A Low-Power and Domain-Specific Reconfigurable FFT Fabric for System-on-Chip Applications
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Multicasting based topology generation and core mapping for a power efficient networks-on-chip
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
BrickX: building hybrid systems for recursive computations
ACM SIGMETRICS Performance Evaluation Review
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Signal processing applications often exhibit substantial parallelism with respect to the number of operations that can be performed independently. However, memory bandwidth and design size present a limiting factor to the speedups that can be achieved. Previous research has focused on bit-serial arithmetic to provide acceleration despite the pin and logic limitations of FPGAs. Conventional bit-serial techniques carry the disadvantage of presenting results in parallel form requiring re-serialization if the results need to be passed to subsequent bit-serial units. This can result in complex control logic, lower performance and, in the case of Xilinx XC4000 FPGAs, inefficient temporary storage structures.This paper presents on-line arithmetic structures tailored for use in the FFT and DCT. Due to their small size, several of these modules can be connected together to form larger, more powerful blocks. The digit-serial nature of on-line arithmetic allows valuable pin resources to feed a larger number of arithmetic units than in the conventional case. Additionally, the resolution of the most significant digit first, a property of on-line arithmetic, allows subsequent calculations to occur at a much earlier stage. As such, performance of the FFT and DCT benefit over conventional and traditional digit-serial FPGA implementations.