Programmable active memories: reconfigurable systems come of age
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Computer organization and design (2nd ed.): the hardware/software interface
Computer organization and design (2nd ed.): the hardware/software interface
SH4 RISC Multimedia Microprocessor
IEEE Micro
The Chimaera reconfigurable functional unit
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Garp: a MIPS processor with a reconfigurable coprocessor
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
MorphoSys: A Reconfigurable Architecture for Multimedia Applications
SBCCI '98 Proceedings of the 11th Brazilian Symposium on Integrated circuit design
IEEE Transactions on Education
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This paper describes an FPGA implementation of a 32-bit processor core, together with a set of tools developed to support the design of processor cores for reconfigurable computing. The basic architecture is a subset of the MIPS16 ISA, which is a 16-bit version of the MIPS architecture aimed at embedded systems. The tools constitute a computer architect workbench allowing for the definition of new instructions through the specification of the microprograms to implement them, the simulation of step-by-step instruction execution with the visualization of the control signals generated and the corresponding data flow in the datapath.