An efficient implementation of Boolean functions nd finite state machine as self-timed circuit
ACM SIGARCH Computer Architecture News
Circuit complexity: from the worst case to the average case
STOC '94 Proceedings of the twenty-sixth annual ACM symposium on Theory of computing
Programmable active memories: reconfigurable systems come of age
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of the ACM (JACM)
The Average Case Complexity of the Parallel Prefix Problem
ICALP '94 Proceedings of the 21st International Colloquium on Automata, Languages and Programming
On the Complexity of Worst Case and Expected Time in a Circuit
STACS '96 Proceedings of the 13th Annual Symposium on Theoretical Aspects of Computer Science
Average Case Complexity of Unbounded Fanin Circuits
COCO '00 Proceedings of the 15th Annual IEEE Conference on Computational Complexity
Computational Aspects of VLSI
A Regular Layout for Parallel Adders
IEEE Transactions on Computers
The average time complexity to compute preffix functions in processor networks
STACS'99 Proceedings of the 16th annual conference on Theoretical aspects of computer science
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We investigate average efficient adders for grid-based environments related to current Field Programmable Gate Arrays (FPGAs) and VLSI-circuits. Motivated by current trends in FPGA hardware design we introduce a new computational model, called the λ -wired grid model. The parameter λ describes the degree of connectivity of the underlying hardware. This model covers among others two-dimensional cellular automata for λ = 0 and VLSI-circuits for λ = 1. To formalize input and output constraints of such circuits we use the notion of input and output schemas. It turns out that the worst case time and area complexity are highly dependent on the specific choice of I/O schemas. We prove that a set of regular schemas supports efficient algorithms for addition where time and area bounds match lower bounds of a broad class of I/O schemas. We introduce new schemas for average efficient addition on FPGAs and show that addition can be done in expected time O(log log n) for the standard VLSI model and in expected time O(√log n) in the pure grid model. Furthermore, we investigate the rectangular area needed to perform addition with small error probability, called area with high probability. Finally, these results are generalized to the class of prefix functions.