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Self-timed logic provides a method for designing logic circuits such that their correct behavior depends neither on the speed of their components nor on the delay along the communication wires. General synthesis methods for efficiently implementing self-timed combinational logic (CL) and finite state machines (FSM) are presented. The resulting CL is shown to require less gates than other proposed methods. The FSM is implemented by interconnecting a CL module with aself-timed master-slave register. The FSM synthesis method is also compared with other approaches. A formal system of behavioral sequential constraints is presented for each of the systems, and their behavior is proven correct. Thus, the synthesized CLs and FSMs can serve as "correct-by-construction" building blocks for self-timed silicon system compilation.