Learning Hardware Using Multiple-Valued Logic, Part 2: Cube Calculus and Architecture

Authors:
Marek Perkowski;David Foote;Qihong Chen;Anas Al-Rabadi;Lech Jozwiak
Affiliations:
-;-;-;-;-
Venue:
IEEE Micro
Year:
2002

Citing 1
Cited 3

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Abstract

A massively parallel reconfigurable processor speeds up logic operators performed in learning hardware. The approach uses combinatorial synthesis methods developed within the framework of the logic synthesis approach in digital-circuit-design automation.