A 32-bit binary floating point neuro-chip

Authors:
Keerthi Laal Kala;M. B. Srinivas
Affiliations:
International Institute of Information Technology, Hyderabad, India;International Institute of Information Technology, Hyderabad, India
Venue:
ICNC'05 Proceedings of the First international conference on Advances in Natural Computation - Volume Part III
Year:
2005

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Abstract

The need for high precision calculations in various scientific disciplines has led to development of systems with various solutions specific to the problem on hand. The complexity of such systems not withstanding, a generic solution could be the use of neural networks. To be able to leverage the best out of the neural network, hardware implementations are ideal as they give speed-up of several orders of magnitude over software simulations. A simple architecture for such a neuro-chip is proposed in this paper. The neuro-chip supports the current draft version of the IEEE-754 standard for floating-point arithmetic. The synthesis results indicate an estimated 84 MCUPS speed of operation.