Parallel Genetic Simulated Annealing: A Massively Parallel SIMD Algorithm
IEEE Transactions on Parallel and Distributed Systems
Solving the error correcting code problem with parallel hybrid heuristics
Proceedings of the 2004 ACM symposium on Applied computing
Closing the Gap: CPU and FPGA Trends in Sustainable Floating-Point BLAS Performance
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
How to Solve It: Modern Heuristics
How to Solve It: Modern Heuristics
Computer Organization and Design, Fourth Edition, Fourth Edition: The Hardware/Software Interface (The Morgan Kaufmann Series in Computer Architecture and Design)
Reconfigurable Computing: Accelerating Computation with Field-Programmable Gate Arrays
Reconfigurable Computing: Accelerating Computation with Field-Programmable Gate Arrays
A flexible on-chip evolution system implemented on a xilinx Virtex-II pro device
ICES'05 Proceedings of the 6th international conference on Evolvable Systems: from Biology to Hardware
Journal of Systems Architecture: the EUROMICRO Journal
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This paper presents a circuit that aids to accelerate the design of good error correcting codes in communications, where this design is a large optimization problem. The binary linear block codes detects and/or corrects the errors occurred during the data transmission. The problem to find a code that corrects a maximum number of errors is an optimization problem usually tackled by means of evolutionary algorithms and massive parallel computations. The circuit has been implemented on FPGA devices due to the easiness of the reconfigurable hardware to support real parallelism. The obtained results show that parallelizing the arithmetic operations involved in the fitness function improves the performance of a custom hardware solution in contrast to a software solution running on CPUs.