Evolution of Parallel Cellular Machines: The Cellular Programming Approach
Evolution of Parallel Cellular Machines: The Cellular Programming Approach
Proceedings of the First International Conference on Evolvable Systems: From Biology to Hardware
ICES '96 Proceedings of the First International Conference on Evolvable Systems: From Biology to Hardware
Proceedings of the Second International Conference on Evolvable Systems: From Biology to Hardware
ICES '98 Proceedings of the Second International Conference on Evolvable Systems: From Biology to Hardware
Fine-Grained Parallel Genetic Algorithms
Proceedings of the 3rd International Conference on Genetic Algorithms
Fast Adaptive Image Processing in FPGAs Using Stack Filters
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
A Pipelined Hardware Implementation of Genetic Programming Using FPGAs and Handel-C
EuroGP '02 Proceedings of the 5th European Conference on Genetic Programming
A flexible on-chip evolution system implemented on a xilinx Virtex-II pro device
ICES'05 Proceedings of the 6th international conference on Evolvable Systems: from Biology to Hardware
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Evolutionary algorithms are useful optimization tools but are very time consuming to run. We present a self-contained FPGA-based implementation of a spatially-structured evolutionary algorithm that provides significant speedup over conventional serial processing in three ways: (a) eficient hardware-pipelined fitness evaluation of individuals, (b) evaluation of an entire population of individuals in parallel, and (c) elimination of slow off-chip communication. We demonstrate using the system to solve a non-trivial signal reconstruction problem using a non-linear digital filter on a Xilinx Virtex FPGA, and find a speedup factor of over 1000 compared to a C implementation of the same system. The general principles behind the system are very scalable, and as FPGAs become even larger in the future, similar systems will provide extremely large speedups over serial processing.