Hardware fault-tolerance within the POEtic system
ICES'05 Proceedings of the 6th international conference on Evolvable Systems: from Biology to Hardware
Parallel algorithm for evolvable-based boolean synthesis on GPUs
Analog Integrated Circuits and Signal Processing
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In this paper we explain how the POEtic chip can be usedfor rapid prototyping. The POEtic chip, currently in the testphase, is a system-on-chip (SoC) containing a microprocessorand a reconfigurable array. Special features allow thedynamic creation of data paths in the reconfigurable arrayat runtime. It has been specially designed to ease the developmentof bio-inspired systems such as neural networks,but can serve as a general purpose platform, or as a prototypefor hardware/software codesign. An AMBA bus allowsPOEtic chips to be connected to each other, or to externaldevices. After describing the hardware SoC, we discussthe software tools that have been created to design andtest different applications. Three of these applications aredescribed in order to demonstrate the utility of the POEticchipýs special features.