Energy-performance tradeoffs in processor architecture and circuit design: a marginal cost analysis
Proceedings of the 37th annual international symposium on Computer architecture
An integrated framework for joint design space exploration of microarchitecture and circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Exploring the fidelity-efficiency design space using imprecise arithmetic
Proceedings of the 16th Asia and South Pacific Design Automation Conference
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This paper studies multi-dimensional optimization at both circuit and micro-architecture levels. By formulating and solving the optimization problem with conflicting design objectives and multiple tunable knobs, it is revealed that the 'sensitivity balance' strategy proposed in recent works for performance-energy optimization is a special case of a general multi-dimensional optimization framework. The results derived in this paper help the understanding of efficient trade-off among multiple design objectives with multiple knobs. The example of an industrial control logic implemented in PLA shows 22% energy saving and 70% area reduction at the expense of 4% delay increase.