Proceedings of the 2002 international symposium on Low power electronics and design
Design of pipeline analog-to-digital converters via geometric programming
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
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An energy optimization is proposed that addresses the non-trivial digital contribution to power and impact on performance in high-speed mixed-signal circuits. Parallel energy and behavioral models are used to quantify architectural tradeoffs across the analog/digital boundary. An interleaved ADC is optimized as a case study to demonstrate this approach. The chosen operating point of 36 channels and 700mV operation gives a 3× improvement in energy compared to the seed of the model. The model matches closely the measured results of an ADC testchip implemented in a 65nm CMOS process.