System-level power optimization: techniques and tools
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Filtering Memory References to Increase Energy Efficiency
IEEE Transactions on Computers
System-level power optimization: techniques and tools
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Synthesis of application-specific memories for power optimization in embedded systems
Proceedings of the 37th Annual Design Automation Conference
A recursive algorithm for low-power memory partitioning
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
From architecture to layout: partitioned memory synthesis for embedded systems-on-chip
Proceedings of the 38th annual Design Automation Conference
A system-level energy minimization approach using datapath width optimization
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Layout-driven memory synthesis for embedded systems-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reducing access energy of on-chip data memory considering active data bitwidth
Proceedings of the 2002 international symposium on Low power electronics and design
ACM Transactions on Embedded Computing Systems (TECS)
Power-Performance Modeling and Tradeoff Analysis for a High End Microprocessor
PACS '00 Proceedings of the First International Workshop on Power-Aware Computer Systems-Revised Papers
IBM Journal of Research and Development
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In this paper, we present the characterization and design of energy-efficient, on chip cache memories. The characterization of power dissipation in on-chip cache memories reveals that the memory peripheral interface circuits and bit array dissipate comparable power. To optimize performance and power in a processor's cache, a multidivided module (MDM) cache architecture is proposed to conserve energy in the bit array as well as the memory peripheral circuits. Compared to a conventional, nondivided, 16-kB cache, the latency and power of the MDM cache are reduced by a factor of 1.9 and 4.6, respectively. Based on the MDM cache architecture, the energy efficiency of the complete memory hierarchy is analyzed with respect to cache parameters in a multilevel processor cache design. This analysis was conducted by executing the SPECint92 benchmark programs with the miss ratios for reduced instruction set computer (RISC) and complex instruction set computer (CISC) machines.