Power Switch Network Design for MTCMOS

• Authors: Ramaprasath Vilangudipitchai;Poras T. Balsara
• Venue: VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
• Year: 2005

Multi-threshold CMOS (MTCMOS) has been a proven methodology to reduce leakage power in DSM designs. Previously lumped sleep transistors were designed for worst case condition, and hence occupied a large area. To reduce the area, Cluster based sleep transistor design was proposed which takes into account simulataneous switching within the circuit blocks. In this paper, we propose an improved method of clustering the sleep transistors by taking on chip decoupling capacitances into account. With the proposed heuristic, we are able to obtain sleep transistor area reduction of 64% with respect to conventional clustering methodology. The leakage current reduction for the circuit blocks is in the order of 2000X to 8000X with respect to the ones without sleep transistors. We propose gate clustering based on ATPG vectors to handle large design. The experimental results are shown for ISCASý85 benchmarks.