Predicting short circuit power from timing models
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Transistor level gate modeling for accurate and fast timing, noise, and power analysis
Proceedings of the 45th annual Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a study on accuracy analysis of power models used for high-level power analysis in a chip design. The purpose is to find factors that are not modeled properly or not yet put into consideration. Different methods of characterizing input capacitance, effects of previous input states and input curves are discussed based on the comparisons with SPICE simulation results using 90nm bulk CMOS and 32nm Metal Gate/High-K Predictive Technology Model (PTM) models.