Balancing System Level Pipelines with Stage Voltage Scaling

Authors:
Hui Guo;Sri Parameswaran
Affiliations:
University of New South Wales;University of New South Wales
Venue:
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Year:
2005

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Abstract

This paper presents an approach to dynamically balance the pipeline by scaling the stage supply voltages. Simulation results show that by such an approach about 50% improvement in throughput and response time, and 11% improvement in power consumption can be achieved with limited memory overhead.