Specification partitioning for system design
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Specification and design of embedded systems
Specification and design of embedded systems
Software estimation from executable specifications
Journal of Computer and Software Engineering - Special issue: hardware-software codesign
Hardware-Software Cosynthesis for Digital Systems
IEEE Design & Test
Hardware-Software Cosynthesis for Microcontrollers
IEEE Design & Test
System-level codesign of mixed hardware-software systems
System-level codesign of mixed hardware-software systems
A scheduling and pipelining algorithm for hardware/software systems
ISSS '97 Proceedings of the 10th international symposium on System synthesis
RECOD: a retiming heuristic to optimize resource and memory utilization in HW/SW codesigns
Proceedings of the 6th international workshop on Hardware/software codesign
A tool for partitioning and pipelined scheduling of hardware-software systems
Proceedings of the 11th international symposium on System synthesis
A system-level synthesis algorithm with guaranteed solution quality
DATE '00 Proceedings of the conference on Design, automation and test in Europe
An algorithm for synthesis of large time-constrained heterogeneous adaptive systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A detailed cost model for concurrent use with hardware/software co-design
Proceedings of the 39th annual Design Automation Conference
Balancing System Level Pipelines with Stage Voltage Scaling
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
MultiMaKe: Chip-multiprocessor driven memory-aware kernel pipelining
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
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For a given throughput constrained system-level specification,we present a design flow and an algorithm to select software(general purpose processors) and hardware components,and then partition and pipeline the specification amongstthe selected components.This is done so as to beat satisfythe throughput constraint at minimal hardware cost.Ourability to pipeline the design at several levels, enables us toattain high throughput designs, and also distinguishes ourwork from previously proposed hardware/software partitioning algorithms.