Heterogeneous multiprocessor implementations for JPEG:: a case study
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Design methodology for pipelined heterogeneous multiprocessor system
Proceedings of the 44th annual Design Automation Conference
Architectural exploration of heterogeneous multiprocessor systems for JPEG
International Journal of Parallel Programming - Special Issue on Multiprocessor-based embedded systems
Synthesis of heterogeneous pipelined multiprocessor systems using ILP: jpeg case study
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
A design flow for application specific heterogeneous pipelined multiprocessor systems
Proceedings of the 46th Annual Design Automation Conference
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-power adaptive pipelined MPSoCs for multimedia: an H.264 video encoder case study
Proceedings of the 48th Design Automation Conference
Hi-index | 0.00 |
With the recent increase of multimedia contents using JPEG and MPEG, low cost, low power consumption and high performance processors for multimedia application have been expected. Particularly, single chip multiprocessor architecture having simple processor cores that will attain good scalability and cost effectiveness is attracting much attention. To exploit full performance of single chip multiprocessor architecture, multigrain parallel processing, which exploits coarse grain task parallelism, loop parallelism and instruction level parallelism, is attractive. This paper describes a multigrain parallel processing scheme for the JPEG encoding on a single chip multiprocessor and its performance. The evaluation shows an OSCAR type single chip multiprocessor having four single-issue simple processor cores gave us 3.59 times speed-up against sequential execution time.