Hardware-software cosynthesis of multi-mode multi-task embedded systems with real-time constraints
Proceedings of the tenth international symposium on Hardware/software codesign
DVS for buffer-constrained architectures with predictable QoS-energy tradeoffs
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A control theoretic approach to energy-efficient pipelined computation in MPSoCs
ACM Transactions on Embedded Computing Systems (TECS) - Special Section LCTES'05
Energy-Aware Scheduling for Streaming Applications on Chip Multiprocessors
RTSS '07 Proceedings of the 28th IEEE International Real-Time Systems Symposium
Network calculus: a theory of deterministic queuing systems for the internet
Network calculus: a theory of deterministic queuing systems for the internet
Low-power adaptive pipelined MPSoCs for multimedia: an H.264 video encoder case study
Proceedings of the 48th Design Automation Conference
Combining optimistic and pessimistic DVS scheduling: an adaptive scheme and analysis
Proceedings of the International Conference on Computer-Aided Design
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
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Pipelined computing is a promising paradigm for embedded system design. Designing the scheduling policy for a pipelined system is however more involved. In this paper, we study the problem of the energy minimization for coarse-grained pipelined systems under hard real-time constraints and propose a method based on an inverse use of the pay-burst-only-once principle. We formulate the problem by means of the resource demands of individual pipeline stages and solve it by quadratic programming. Our approach is scalable w.r.t the number of the pipeline stages. Simulation results using real-life applications as well as commercialized processors are presented to demonstrate the effectiveness of our method.