Hardware architecture design of an H.264/AVC video codec
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A power-efficient and self-adaptive prediction engine for H.264/AVC decoding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Consumer Electronics
An AVS HDTV video decoder architecture employing efficient HW/SW partitioning
IEEE Transactions on Consumer Electronics
H.264/AVC baseline profile decoder complexity analysis
IEEE Transactions on Circuits and Systems for Video Technology
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AVS (audio video coding standard) is the latest multimedia coding standard of China. Similar to H.264/AVC, AVS adopted the technology of fractional-pel-accurate motion compensation, which enhanced the compression efficiency. To obtain fractional pels, 4-tap FIR filters and bilinear filters are used for luma and chroma interpolation respectively. Unlike the VLSI-optimized FIR filters which could be implemented by adders and shifters, the bilinear filter for chroma is not so convenient for direct VLSI implementation due to its multiplications. In this paper, we propose a VLSI-oriented algorithm named SHAM (x-y-separated halved-approaching method) to accomplish the bilinear filtering. The proposed SHAM algorithm adopts a halved-approaching method which is an addition-and-shift-only method and with simpler data path. VLSI structures are also provide to implement the SHAM algorithm in this paper. Experiments based on UMC 0.18@mm process show that the SHAM algorithm could be implemented with about 48% less silicon area or at doubled frequency compared with the direct implementation of the bilinear filter.