An H.264/SVC memory architecture supporting spatial and course-grained quality scalabilities

Authors:
Niranjan D. Narvekar;Bharatan Konnanath;Shalin Mehta;Santosh Chintalapati;Ismail AlKamal;Chaitali Chakrabarti;Lina J. Karam
Affiliations:
Department of Electrical Engineering, Arizona State University, Tempe, AZ;Department of Electrical Engineering, Arizona State University, Tempe, AZ;Department of Electrical Engineering, Arizona State University, Tempe, AZ;Department of Electrical Engineering, Arizona State University, Tempe, AZ;Department of Electrical Engineering, Arizona State University, Tempe, AZ;Department of Electrical Engineering, Arizona State University, Tempe, AZ;Department of Electrical Engineering, Arizona State University, Tempe, AZ
Venue:
ICIP'09 Proceedings of the 16th IEEE international conference on Image processing
Year:
2009

Citing 6
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Abstract

The standardized Scalable Video Coding (SVC) extension of H.264/AVC achieves significant improvements in coding efficiency relative to the scalable profiles of prior video coding standards, but its computational complexity and memory access requirements make the design of a low power hardware architecture a challenging task. This paper presents an SVC decoder architecture supporting spatial and coarse-grained quality scalability. The architecture optimizes the size of the on-chip memory and reduces the powerconsuming and time-intensive external memory accesses.