Customizing wide-SIMD architectures for H.264

Authors:
S. Seo;M. Woh;S. Mahlke;T. Mudge;S. Vijay;C. Chakrabarti
Affiliations:
Department of Electrical and Computer Engineering, University of Michigan, Ann Arbor, MI;Department of Electrical and Computer Engineering, University of Michigan, Ann Arbor, MI;Department of Electrical and Computer Engineering, University of Michigan, Ann Arbor, MI;Department of Electrical and Computer Engineering, University of Michigan, Ann Arbor, MI;Department of Electrical Engineering, Arizona State University, Tempe, AZ;Department of Electrical Engineering, Arizona State University, Tempe, AZ
Venue:
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
Year:
2009

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Abstract

In recent years, the mobile phone industry has become one of the most dynamic technology sectors. The increasing demands of multimedia services on the cellular networks have accelerated this trend. This paper presents a low power SIMD architecture that has been tailored for efficient implementation of H.264 encoder/decoder kernel algorithms. Several customized features have been added to improve the processing performance and lower the power consumption. These include support for different SIMD widths to increase the SIMD utilization efficiency, diagonal memory organization to support both column and row access, temporary buffer and bypass support to reduce the register file power consumption, fused operation support to increase the processing performance, and a fast programmable crossbar to support complex data permutation patterns. The proposed architecture increases the throughput of H.264 encoder/decoder kernel algorithms by a factor of 2.13 while achieving 29% of energy-delay improvement on average compared to our previous SIMD architecture, SODA.