AnySP: anytime anywhere anyway signal processing
Proceedings of the 36th annual international symposium on Computer architecture
Scalable register bypassing for FPGA-based processors
Microprocessors & Microsystems
Customizing wide-SIMD architectures for H.264
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
ACM Transactions on Embedded Computing Systems (TECS) - Special issue on application-specific processors
Shared-port register file architecture for low-energy VLIW processors
ACM Transactions on Architecture and Code Optimization (TACO)
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With the increase in issue width, bypass control of a processor become more complex. Also, in a processor, operands are read both from register file as well as from bypass. For a multi-port register file, read/write energy is much more than that of single port register file. Both redundant register read/write and bypass control area can be reduced with compiler hints for register bypass. In this work we suggest a innovative way to represent compiler bypass hints that serve both these motivations. Further, bypass hints are used in effective design of multi-stage bypass network. Experiments on mediabench benchmarks show that by using our approach, (i) register file energy savings can be as as much as 60% (ii) and synthesis of VLIW core saves 2-4% of the core area.