A High Performance H.264 Deblocking Filter

Authors:
Vagner Rosa;Altamiro Susin;Sergio Bampi
Affiliations:
Informatics Institute, Federal University of Rio Grande do Sul, Bairro Agronomia - Porto Alegre, Brasil CEP 91501-970 Caixa Postal: 15064;Informatics Institute, Federal University of Rio Grande do Sul, Bairro Agronomia - Porto Alegre, Brasil CEP 91501-970 Caixa Postal: 15064;Informatics Institute, Federal University of Rio Grande do Sul, Bairro Agronomia - Porto Alegre, Brasil CEP 91501-970 Caixa Postal: 15064
Venue:
PSIVT '09 Proceedings of the 3rd Pacific Rim Symposium on Advances in Image and Video Technology
Year:
2009

Citing 3
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Abstract

Although the H.264 Deblocking Filter process is a relatively small piece of code in a software implementation, profile results shows it cost about a third of the total CPU time in the decoder. This work presents a high performance architecture for implementing a H.264 Deblocking Filter IP that can be used either in the decoder or in the encoder as a hardware accelerator for a processor or embedded in a full-hardware codec. A developed IP using the proposed architecture support multiple high definition processing flows in real-time.