High performance architecture of an application specific processor for the H.264 deblocking filter
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The in-loop deblocking filter in H.264/AVC contains highly adaptive processing on both sample level and block edge level, which inevitably appears in the loop kernel of the algorithm. Therefore it is quite difficult to efficiently implement the filter on digital signal processor (DSP) platform. In this paper, deeply pipelined DSP solutions to both edge filter and boundary strength decision are presented. To avoid conditional jumping when performing edge filter, DSP first calculate all possible filtered outputs, then combine them with corresponding masks to get single output for each sample, and last conditionally store the combined output based on the final content activity check result. Moreover, on the basis of the symmetry of filtering on both sides of the edge, two symmetrical samples are packed into one register for "pair processing" to increase the parallelism of the pipeline. While for boundary strength decision, two-pass pipelines are designed. In the first pass, strengths are created by using the inter-relative information on block level, and then in the second pass, these strengths are refined based on the intra mode checks on macroblock level. To cooperate with global filter control and also to keep pipelining, a two-level internal memory organization is presented as well. The simulated results indicate that this efficient implementation can support real-time filtering for high resolution videos