An Efficient Pipeline Architecture for Deblocking Filter in H.264/AVC

Authors:
Chung-Ming Chen;Chung-Ho Chen
Affiliations:
The authors are with the Department of Electrical Engineering, National Cheng Kung University, Taiwan. E-mail: cmchen@ee.ncku.edu.tw, E-mail: chchen@mail.ncku.edu.tw;The authors are with the Department of Electrical Engineering, National Cheng Kung University, Taiwan. E-mail: cmchen@ee.ncku.edu.tw, E-mail: chchen@mail.ncku.edu.tw
Venue:
IEICE - Transactions on Information and Systems
Year:
2007

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Proceedings of the 21st annual symposium on Integrated circuits and system design
Configurable VLSI architecture for deblocking filter in H.264/AVC

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimizing the H.264/AVC Video Encoder Application Structure for Reconfigurable and Application-Specific Platforms

Journal of Signal Processing Systems

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Abstract

In this paper, we study and analyze the computational complexity of deblocking filter in H.264/AVC baseline decoder based on SimpleScalar/ARM simulator. The simulation result shows that the memory reference, content activity check operations, and filter operations are known to be very time consuming in the decoder of this new video coding standard. In order to improve overall system performance, we propose a novel processing order with efficient VLSI architecture which simultaneously processes the horizontal filtering of vertical edge and vertical filtering of horizontal edge. As a result, the memory performance of the proposed architecture is improved by four times when compared to the software implementation. Moreover, the system performance of our design significantly outperforms the previous proposals.