A near optimal deblocking filter for H.264 advanced video coding
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Journal of Signal Processing Systems
Deblocking Filter Algorithm with Low Complexity for H.264 Video Coding
PCM '08 Proceedings of the 9th Pacific Rim Conference on Multimedia: Advances in Multimedia Information Processing
A Multi-core Architecture Based Parallel Framework for H.264/AVC Deblocking Filters
Journal of Signal Processing Systems
Low-power H.264 video compression architectures for mobile communication
IEEE Transactions on Circuits and Systems for Video Technology
Methods for Power/Throughput/Area Optimization of H.264/AVC Decoding
Journal of Signal Processing Systems
A two-result-per-cycle deblocking filter architecture for QFHD H.264/AVC decoder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we proposed a platform based bus-interleaved architecture for the de-blocking filter in H.264. Specifically, to efficiently use the bus bandwidth, we classify the filtering mode into 8 types and use an adaptive transmission scheme to avoid redundant data transfer. Moreover, to reduce the processing latency, we use a bus-interleaved architecture for conducting data transmission and parallel filtering. As compared to the state-of-the-art designs, our scheme offers 1.6x to 7x performance improvement. While clocking at 100 MHz, our design can support 2560×1280 @ 30 Hz processing throughput. The proposed design is suitable for low cost and real-time applications. Moreover, it can be easily applied in system-on-chip design.